ACM International Conference on
Computing Frontiers
Ischia, Italy
May 2-5, 2006

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Keynote Address 1
May 3, 2006
9:00a - 10:00a
Chip Multiprocessing and the Cell Broadband Engine
Michael Gschwind, IBM T.J. Watson Research Center, Yorktown Heights, NY US


Chip multiprocessing has become an exciting new direction for system designers to deliver increased performance by exploiting CMOS scaling. We discuss key design decisions facing the system architect of a chip multiprocessor and describe how these choices were made in the design of the Cell Broadband Engine™.

An important decision is whether to base system performance on thread-level parallelism alone, or to complement thread-level parallelism with other forms of parallelism. Depending on workload characteristics, providing parallelism at the processor core level may increase overall system efficiency.

Parallelism is also a key to utilize available memory bandwidth more efficiently, by overlapping and interleaving multiple accesses to system memory. By interleaving the access streams of multiple threads, memory level parallelism can be increased to allow better memory interface utilization. In addition, compute-transfer parallelism (CTP) offers a new form of parallelism to initiate memory transfers under software control without stalling the requesting thread.

We describe how the Cell Broadband Engine™ uses parallelism at all levels of the system abstraction to deliver a quantum leap in application performance, and how the Cell Synergistic Memory Flow engine exploits compute-transfer level parallelism by providing efficient block transfer capabilities.

Biography: Dr. Michael Gschwind is an IBM Master Inventor, and an architect and a logic design lead for a future IBM System. He was one of the initiators and a leading contributor to the Cell Broadband Engine system architecture definition as well as a lead architect for the definition of the Synergistic Processor architecture. During the definition of the Synergistic Processor architecture, Michael also developed the first Cell Broadband Engine compiler.

Michael joined the IBM TJ Watson Research Center, Yorktown Heights, NY, in 1997. He has held leadership positions in several seminal projects, including the DAISY dynamic compilation project where he was a lead architect for the BOA high-frequency statically scheduled architecture, and was a leading contributor to the development of pioneering dynamic compilation techniques. Michael was also a leading contributor to seminal work on power/performance trade-offs in microprocessor designs which formalized the futility of the frequency-centric uniprocessor design approach used in the industry at the time, an insight that had already guided the design of the Cell Broadband Engine.

Michaels contributions to IBM systems and technology have been recognized with several corporate awards. In addition to his contributions to the design and implementation of IBM systems, he is the author of over 75 papers, covering hardware/software co-design, compiler technology, multimedia processing, and high-performance computer architecture, and has received key patents for his inventions in these areas.

In addition to his corporate contributions, Michael has been a faculty member at Technische Universitat Wien, Vienna, Austria, and a visiting faculty member at Princeton University where he has taught classes on advanced computer architecture. Michael received PhD and Dipl.-Ing. degrees in computer science from Technische Universitat Wien, Vienna, Austria.