Full Paper	25 min
Short Paper	10 min
DAY 1
10:30--11:45
Main-A		Distributed Systems and Networking Frontiers
46	10:30	A Novel Multi-Winner Auction-based Transaction Mechanism for Blockchain Storage Networks
143	10:55	FractalSync: Lightweight Scalable Global Synchronization of Massive Bulk Synchronous Parallel AI Accelerators
41	11:05	NeurDORA: Neural-Aided Decentralized Offloading Based on Resource Auction
84	11:15	Enabling the Proxy Computing Paradigm on DPU-based FPGA Acceleration
70	11:25	Flex8: A Flexible Precision Co-design for 8-bit Neural Network
11:45--13:00
Main-B		Pushing the Boundaries of Cross-cutting Computing Challenges
73	11:45	Accordion: A malleable pipeline scheduling approach for adaptive SLO-aware inference serving
32	12:10	PowerSecBench: reveal microarchitectural power leakages using generic RISC-V microbenchmarks
18	12:35	FERIVer: An FPGA-assisted Emulated Framework for RTL Verification of RISC-V Processors
56	12:45	Charactering and Mitigating Performance Variability in Parallel Applications on Modern HPC Clusters
14:00-15:15
Main-C		System Software and Runtime Frontiers
110	14:00	Pattern Matching, Transformation and Code Replacement on a Polyhedral Representation of Nested Loops
123	14:25	Multi-GPU Greedy Scheduling Through a Polyglot Runtime
55	14:50	SRBB-based Quantum State Preparation
1	15:00	RapidChiplet: A Toolchain for Rapid Design Space Exploration of Inter-Chiplet Interconnects
15:30--16:45
Main-D		Hardware Frontiers
3	15:30	AdaTP: Enhancing Temporal Prefetching with Adaptive Metadata Filtering
27	15:55	Combination of Storage and Accumulation for Synchronous SpMV Acceleration on FPGAs with HBM
99	16:20	Computing Efficiency Improvement for Multi-PEA CGRA with Built-in Control Design
DAY 2
10:00--11:15
Main-F		Best Papers
66	10:00	Ramping Up Open-Source RISC-V Cores: Assessing the Energy Efficiency of Superscalar, Out-of-Order Execution
48	10:25	Register Dispersion: Reducing the Footprint of the Vector Register File in Vector Engines of Low-Cost RISC-V CPUs
129	10:50	Solution of Backtracking Problems on Tile-Centric AI Accelerators
11:15--12:30
Main-G		Systems for AI
44	11:15	Logic Gate Network Inference Acceleration with RISC-V Custom Instruction Set
104	11:40	A Custom RISC-V ISA with Scalable Processing Units for Efficient Neural Network Inference
17	12:05	FastSpMM: Leveraging Tensor Cores for Sparse Matrix Multiplication
14:00--15:15
Special Session		Analog Computing / ChipsAct
	14:00	Solving Partial Differential Equations on an Analog, Optical Platform	Chene Tradonsky, Omri Wolf, Talya Vaknin, Dan Glück, Dov Furman
	14:25	Photonic computing with Lithium Niobate integrated Photonics – from Concepts to Products	Victor Brasch
	14:50	The U.S. Microelectronics Research Programs and Where They Lower Barriers to Co-Design	James A. Ang, Antonino Tumeo, Nicolas Bohm Agostini, Ankur Limaye
15:30--16:45
Special Session		CompSpace
	15:30	Coordinating Instruments for Multi-Messenger Astrophysics	Daisy Wang, Ye Htet, Marion Sudvarg, Roger Chamberlain, Jeremy Buhler, James Buckley
	15:55	Mitigating Cross-Domain SEU Corruption in FPGA-Based AI Accelerators for Space Applications	Sarah Azimi, Eleonora Vacca, Corrado De Sio, Luca Sterpone
	16:20	Cutting-Edge Strategies for Radiation Effect Estimation on Asteroids Space Mission	Eleonora Vacca, Sarah Azimi, Luca Sterpone
DAY 3
10:30--11:30
Main-H		Memory Frontiers
11	10:30	CVA6-VMRT: A Modular Approach Towards Time-Predictable Virtual Memory in a 64-bit Application Class RISC-V Processor
81	10:55	Corrosion Hammer: A Self-Activated Bit-Flip Attack to the Processing-In-Memory Accelerator
52	11:20	Enhancing Practicality of Memory Compression for GPUs with High-Throughput Simplifications
11:30--13:00
Main-I		Crosscutting Developments and Hardware Frontiers
72	11:30	Multi-Task Collaborative Learning for Robust Diabetic Retinopathy Grading on Low-Quality Fundus Images
97	11:55	MCCNet: Multi-Scale Context Cross-Attention Network for Diabetic Retinopathy classification
67	12:20	Unleashing Optimization in Dynamic Circuits through Branch Expansion
124	12:45	Quantum Circuit Design for Finding k-Cliques via Quantum Amplitude Amplification Strategies