| 8:30 | 8:45 | Opening / Welcome | |
| 8:45 | 10:00 | Keynote: Towards Truly Integrated Photonic and Electronic Computing | Moray McLaren, (HP Labs) |
| 10:00 | 10:30 | Break | |
| 10:30 | 12:30 | Session 1: Computing At the Frontier | Chair: Carsten Trinitis |
| Algorithmic Methodologies for Ultra-efficient Inexact Architectures for Sustaining Technology Scaling | Avinash Lingamneni (Rice University, USA & CSEM SA, Switzerland), Kirthi Krishna Muntimadugu (Rice University, USA), Christian Enz (CSEM SA & EPFL, Switzerland), Richard M. Karp (University of California at Berkeley, USA), Krishna Palem (Rice University, USA & Nanayang Technological University, Singapore), and Christian Piguet (CSEM SA, Switzerland) | ||
| A Reconfigurable Optical/Electrical Interconnect Architecture for Large-scale Clusters and Datacenters | Diego Lugones (Rince Institute. Dublin City University), Kostas Katrinis (Dublin Research Lab, IBM Research), and Martin Collier (Rince Institute. Dublin City University) | ||
| BSArc: Blacksmith Streaming Architecture for HPC Accelerators | Muhammad Shafiq (Barcelona Supercomputing Center), Miquel Pericas (Tokyo Institute of Technology), and Nacho Navarro and Eduard Ayguade (Barcelona Supercomputing Center) | ||
| A Limits Study of Benefits from Nanostore-Based Future Data-Centric System Architectures | Jichuan Chang and Kevin T. Lim (HP Labs), Trevor Mudge (University of Michigan), Parthasarathy Ranganathan (HP Labs), David Roberts (Micron Technologies), and Mehul A. Shah (Nou Data) | ||
| 12:30 | 14:00 | Lunch Break (Not provided) | |
| 14:00 | 16:00 | Session 2: Compilation, Programming and Runtime Systems | Chair: Josef Weidendorfer |
| Compile-Time Loop Fusion for Unstructured Mesh Applications | Carlo Bertolli, Adam Betts, and Paul Kelly (Imperial College London), Gihan Mudalige (Oxford e-Research Centre), and Mike Giles (Oxford University) | ||
| GA-GPU: Extending a Library-based Global Address Space Programming Model for Scalable Heterogeneous Computing Systems | Vinod Tipparaju (AMD) and Jeff Vetter (ORNL) | ||
| SnCTM: Reducing False Transaction Aborts by Adaptively Changing the Source of Conflict Detection | Isuru Herath, Demian Rosas, Mikel Lujan, and Ian Watson (The University of Manchester) | ||
| Architectural Support of Multiple Hypervisors over Single Platform for Enhancing Cloud Computing Security | Weidong Shi (University of Houston), Taeweon Suh (Korea Univeristy), JongHyuk Lee (University of Houston), DongHyuk Woo (Intel), and Xinwen Zhang (Huawei) | ||
| 16:00 | 16:30 | Break | |
| 16:30 | 18:30 | Session 3: Memory Systems | Chair: Vinod Tipparaju, AMD |
| SuperCoP: A General, Correct, and Performance-efficient Supervised Memory System | Bharghava Rajaram, Vijay Nagarajan, Andrew Mcpherson and Marcelo Cintra (Institute for Computing Systems Architecture, University of Edinburgh) | ||
| Exploring Latency-Power Tradeoffs in Deep Nonvolatile Memory Hierarchies | Doe Hyun Yoon, Tobin Gonzalez, Parthasarathy Ranganathan, and Robert S. Schreiber (HP Labs) | ||
| The Tradeoffs of Fused Memory Hierarchies in Heterogeneous Architectures | Kyle Spafford, Jeremy S. Meredith, Seyong Lee, Dong Li, Philip C. Roth, and Jeffrey S. Vetter (ORNL) | ||
| DMA-circular: An Enhanced High Level Programmable DMA Controller for Optimal Management Of On-chip Local Memories | Nikola Vujic, Lluc Alvarez Martí, Marc Gonzalez, Xavier Martorell, and Eduard Ayguade (Barcelona Supercomputing Center) | ||
| 9:00 | 10:30 | Session on Computer Intelligence in Games | Session on Exascale in Europe |
| Daniele Loiacono (Politecnico di Milano) Georgios Yannakakis (University of Copenhagen) |
Adam Carter (University of Edinburgh) Roberto Giorgi (University of Siena) |
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| 10:30 | 11:00 | Break | |
| 11:00 | 12:30 | Session on Computer Intelligence in Games | Session on Exascale in Europe |
| Simon Lucas (University of Essex) Kenneth Stanley (University of Central Florida) |
Axel Auweter (Leibniz Computing Centre) Nikola Puzovic (Barcelona Supercomputing Center) |
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| 12:30 | 18:00 | Free Time | |
| 18:00 | 19:00 | Poster Presentations | |
| 19:00 | 20:00 | Poster Session | |
| 20:00 | 22:00 | Banquet | |
| 8:30 | 10:00 | Session 4: Energy Efficiency | Chair: Francesca Palumbo |
| Studying The Impact Of Application-level Optimizations On The Power Consumption Of Multi-Core Architectures | Shah Mohammad Faizur Rahman, Jichi Guo, Akshatha Bhat, Carlos Garcia, Majedul Haque Sujon, and Qingy Yi (University of Texas at San Antonio) and Chunhua Liao and Daniel Quinlan (Lawrence Livermore National Laboratory) | ||
| Improving Energy Efficiency for Mobile Platforms by Exploiting Low-power Sleep States | Alexander W. Min, Ren Wang, James Tsai, Mesut A. Ergin, and Tsung-Yuan Charlie Tai (Intel Labs) | ||
| Improving Coherence Protocol Reactiveness by trading Bandwidth for Latency | Lucía G. Menezo, Valentin Puente, Pablo Abad, and José Ángel Gregorio (University of Cantabria) | ||
| 10:00 | 10:30 | Break | |
| 10:30 | 12:30 | Session 5: Massive Parallelism and Streaming | Chair: Hubertus Franke |
| A Programmable Processing Array Architecture Supporting Dynamic Task Scheduling and Module-Level Prefetching | Junghee Lee and Hyung Gyu Lee (Georgia Institute of Technology), Soonhoi Ha (Seoul National University), Jongman Kim (Georgia Institute of Technology), and Chrysostomos Nicopoulos (University of Cyprus) | ||
| Adaptive Task Duplication Using On-line Bottleneck Detection For Streaming Applications | Yoonseo Choi (IBM), Cheng-Hong Li (unaffiliated), and Dilma Da Silva, Alan Bivens, and Eugen Schenfeld (IBM) | ||
| Concurrent Hybrid Switching for Massively Parallel Systems-on-Chip: the CYBER architecture | Francesca Palumbo, Danilo Pani, Andrea Congiu, and Luigi Raffo (DIEE - University of Cagliari) | ||
| A Hierachical Configuration System for a Massively Parallel Neural Hardware Platform | Francesco Galluppi, Sergio Davies, Alexander D. Rast, Thomas Sharp, Luis A. Plana, and Steve B. Furber (University of Manchester) | ||
| 12:30 | 14:00 | Lunch Break (not provided) | |
| 14:00 | 16:00 | Session 6: Modeling, Benchmarking and Characterization | Chair: Mikel Lujan, University of Manchester |
| Reuse Distance Based Performance Modeling and Workload Mapping | Sai Prashanth Muralidhara, Mahmut Kandemir, and Orhan Kislal (Pennsylvania State University) | ||
| The Boat Hull Model: Enabling Performance Prediction for Parallel Computing Prior to Code Development | Cedric Nugteren and Henk Corporaal (Eindhoven University of Technology) | ||
| Parameterized Micro-benchmarking: An Auto-tuning Approach for Complex Applications | Wenjing Ma and Sriram Krishnamoorthy (PNNL) and Gagan Agrawal (Ohio State University) | ||
| A Flexible OS-based Approach for Characterizing Solid-state Disks' Endurance | Gokul B. Kandiraju and Kaoutar El Maghraoui (IBM T.J Watson Research Center) | ||
| 16:00 | 16:15 | Closing | |
| Title | Authors |
| An Out-of-Order Vector Processing Mechanism for Multimedia Applications | Ye Gao, Ryusuke Egawa, Hiroyuki Takizawa and Hiroaki Kobayashi(Tohoku University) |
| Towards Player-Driven Procedural Content Generation | Noor Shaker, Georgios N. Yannakakis and Julian Togelius, (IT University of Copenhagen) |
| An Efficient Vectorization of Linked-Cell Particle Simulations | Wolfgang Eckhardt and Alexander Heinecke (TU Munchen) |
| Dynamic Percolation: A case of study on the shortcomings of traditional optimization in Many-core Architectures | Elkin Garcia, Daniel Orozco, Kelly Livingston, Guang R Gao (University of Delaware), Rishi Khan (ET International) and Ioannis E Venetis (University of Patras) |
| CoreSymphony Architecture | Tomoyuki Nagatsuka, Yoshito Sakaguchi and Kenji Kise (Tokyo Institute of Technology) |
| Instructions Activating Conditions for Hardware-Based Auto-Scheduling | Silvia Lovergine and Fabrizio Ferrandi (Politecnico di Milano) |
| Selective Search of Inlining Vectors for Program Optimization | Rosario Cammarota, Alexandru Nicolau, Alexander Veidenbaum, (University of California Irvine) Arun Kejariwal and Debora Donato (Yahoo! Inc.) |
| D3AS Project: a Different Approach to the Manycore Challenges | Lorenzo Verdoscia and Roberto Vaccaro (National Reaseach Council - Italy) |
| A Capacity-Efficient Insertion Policy for Dynamic Cache Resizing Mechanisms | Masayuki Sato, Yusuke Tobo, Ryusuke Egawa, Hiroyuki Takizawa and Hiroaki Kobayashi (Tohoku University) |
| Accelerated High-Performance Computing Through Efficient Multi-Process GPU Resource Sharing | Teng Li, Vikram K Narayana and Tarek El-Ghazawi (The George Washington University) |
| Improving the Performance of k-means Clustering Through Computation Skipping and Data Locality Optimizations | Orhan Kislal, Piotr Berman and Mahmut Kandemir (Pennsylvania State University) |
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