ACM International Conference on Computing Frontiers 2019

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Key Dates Full Papers

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March 4, 2019

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Early Registration Deadline

April 7, 2019
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Author Notification

March 26, 2019

Camera-Ready Papers Due

April 1, 2019

Early Registration Deadline

April 7, 2019
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• Keynote 1: Catherine Graves
  High performance, power efficient hardware accelerators: emerging devices, circuits and architecture co-design
• Keynote 2: Danilo Pau
  Artificial Intelligent Sensors at the core of Cyber-Physical-Systems
  From theory to practical applications

High performance, power efficient hardware accelerators: emerging devices, circuits and architecture co-design

Abstract:
General-purpose digital systems have long benefited from favorable scaling, but performance improvements have slowed dramatically in the last decade. Computing is therefore returning to custom and specialized systems, frequently using heterogeneous accelerators. Particularly driven by the data-centric workloads of machine learning and deep learning, an intense development of conventional accelerators (GPUs, FPGAs, CMOS ASICs) but also unconventional accelerators using novel circuits and devices beyond CMOS is currently underway. In this talk, I will discuss some common characteristics of high-performance and power-efficient accelerators in this diverse space and the ecosystem development (such as new interconnects) needed for them to thrive. To illustrate accelerator characteristics and their potential, I will describe our group’s efforts to co-design from algorithms and architectures down to novel devices for gains in speed and power. We have developed architectures leveraging the analog and non-volatile nature of memristors (tunable resistance switches) assembled in crossbar arrays to accelerate machine learning, image and signal processing. We have also developed new circuits and assembled architectures to accelerate Finite Automata, enabling rapid pattern matching used in applications from security to genomics. Significant improvements over CPUs, GPUs, and custom digital ASICs are forecasted in both such systems, highlighting the potential for unconventional accelerators in future high-performance computing systems.

Bio:
Dr. Catherine Graves is a research scientist at Hewlett Packard Labs in Palo Alto, CA developing analog and neuromorphic computational accelerators which leverage emerging devices such as resistive RAM. These hardware accelerators are designed to overcome the limited energy efficiency and throughput of existing general-purpose digital approaches, particularly for data centric computations, by targeting bottlenecked computations and data movement. Currently, she leads a team developing an accelerator for finite automata, targeting regular expression matching at wire speeds for network intrusion detection systems. Previously, she developed an accelerator utilizing analog resistive RAM devices to natively perform vector-matrix multiplication, accelerating the core computation in wide-ranging applications from neural networks to signal processing. She received her Ph.D. in Applied Physics from Stanford University studying ultrafast magnetism for future magnetic memory technologies. She has published over 30 peer-reviewed papers, three book chapters and has several patent applications pending.

Artificial Intelligent Sensors at the core of Cyber-Physical-Systems
From theory to practical applications

Abstract:
Cyber-Physical Systems (CPS) are becoming, without pace, more pervasive into embedded systems. Artificial Intelligence, Machine Learning and Deep Learning are mostly confined into the cloud, where unlimited computing resources seems to be available and evolving tirelessly. Unfortunately a layered architecture in which dumb sensors are attached to the cloud would become quickly too centralized, poorly scalable and slowly responsive in the IoT expected scenario that will deploy hundreds of billions of sensors communicating through low data rate networks.

In that context, STMicroelectronics is developing solutions to bring Artificial Intelligence closer to the sensors. This talk will review new intelligent technological solutions and mechanisms under development and publicly announced, namely STM32CUBE.AI. The talk will tell how they represent the key ingredients needed to design the current and future generation of artificial intelligent cyber-physical embedded systems and derived applications based on STMicroelectronics heterogeneous sensors, micro controllers and SoCs. In particular, aspects related on how address current interoperability, productivity and constrained embedded resource gaps will be discussed with practical examples based on STM32CUBE.AI. Moreover, the investigation and design of adaptive and cognitive computational-intelligence techniques able to learn, adopting artificial neural networks, and operate in nonstationary environments will be introduced. Finally, the deployment of networked intelligent cyber-physical systems, able to operate in time varying environments, will be also commented.

Bio:
Danilo Pietro Pau graduated at Politecnico di Milano, Italy on 1992 in Electronic Engineering. On 1991 he joined STMicroelectronics and since then worked on different R&D subjects such memory reduced HDMAC and MPEG video decoding, video coding, video transcoding, embedded graphics, computer vision and deep learning in System Research and Applications to bring them into company products. Currently he holds Senior Principal Engineer, Member of Technical Staff position. He founded and served as Chairman of the STMicroelectronics Technical Staff Italian Community. He is also IEEE Fellow, serving into Action for Industry as Industry Ambassador member for IEEE Region 8 South Europe and vice chair of Task Force on "Intelligent Cyber-Physical Systems" within IEEE Computational Intelligence Society.