Final Program

Monday, May 5
Welcome and Opening Remarks by General Chair and Program Co-Chairs
Keynote 1 Scaling Up Next Generation Supercomputers
Valentina Salapura
IBM Master Inventor
IBM T.J. Watson Research Center, USA
Coffee Break
Workshop on “Memory Access on Future Processors: A Solved Problem? [Time: 10:50 - 12:50]
Josef Weidendorfer, Technische Universität München, Germany
Rainer Buchty, Universität Karlsruhe, Germany
Jie Tao, Institute for Scientific Computing Karlsruhe,Germany

SAMS: Single-Affiliation Multiple-Stride Parallel Memory Scheme
Chunyang Gou, Georgi K. Kuzmanov, Georgi N. Gaydadjiev

Modeling and Evaluating Heterogeneous Memory Architectures by Trace-driven Simulation
Wei Wang, Qigang Wang, Wei Wei, Dong Liu

Data and Thread Affinity in OpenMP Programs
Christian Terboven, Dieter an Mey, Henry Jin, Thomas Reichstein

Parallel Matrix Multiplication based on Space-filling Curves on Shared Memory Multicore Platforms
Michael Bader, Alexander Heinecke

Session 1: Innovative Computing Platforms I (Cell) Chair: Fabio Schifano

Accelerating Computing with the Cell Broadband Engine Processor
Catherine Crawford, Paul Henning, Michael Kistler, Cornell Wright

Cell-SWat: Modeling and Scheduling Wavefront Computations on the Cell B/E
Ashwin M. Aji, Wu-chun Feng, Filip Blagojevic, Dimitrios S Nikolopoulos

DMA-based Prefetching for I/O Intensive Workloads on the Cell Architecture
M. Mustafa Rafique, Ali R. Butt, Dimitrios S. Nikolopoulos

Exact Multi-pattern String Matching on the Cell/B.E. Processor
Daniele Paolo Scarpazza, Oreste Villa, Fabrizio Petrini

Lunch Break
Workshop on “Radiation Effects and Fault Tolerance in Nanometer Technologies” Chairs:
Fernanda Lima Kastensmidt, Universidade Federal do Rio Grande do Sul, Brazil
Greg Bronevetsky, Lawrence Livermore National Lab,USA

Quantifying Software Vulnerability
Vilas Sridharan, David R. Kaeli

Analyzing the Effect of Soft Error Rate in the Granularity of Recomputation-based Techniques
Carlos A. L. Lisboa, Fernanda G. L. Kastensmidt, Luigi Carro

Session 2: Programming Models Chair: Keshav Pingali

Principles of a Reversible Programming Language
Tetsuo Yokoyama, Holger Bock Axelsen, Robert Glück

FPGA-based prototype of a PRAM-on-chip processor
Xingzhi Wen, Uzi Vishkin

The Limits of Software Transactional Memory (STM): Dissecting Haskell STM Applications on a Many-Core Environment
Cristian Perfumo, Nehir Sonmez, Srdjan Stipic, Osman Unsal, Adrian Cristal, Tim Harris, Mateo Valero
Efficient Fault Tolerance in Multi-media Applications through Selective Instruction Replication
Ayswarya Sundaram, Ameen Aakel, Derek Lockhart, Darshan Thaker, Diana Franklin

A new Placement Algorithm for the Optimization of Fault Tolerant Circuits on Reconfigurable Devices
Luca Sterpone, Niccolò Battezzati, Massimo Violante

Yield Improvement and Power Aware Low Cost Memory Chips
Costas Argyrides, Stephania Loizidou Himona, Dhiraj K. Pradhan

Session 3: HPC Chair: Valentina Salapura

A Study of the Effects of Machine Geometry and Mapping on Distributed Transpose Performance
Maria Eleftheriou, Blake G. Fitch, Aleksandr Rayshubskiy, T.J. Christopher Ward, Phillip Heidelberger, Robert S. Germain

Optimizing Sparse Matrix-Vector Multiplication Using Index and Value Compression
Kornilios Kourtis, Georgios Goumas, Nectarios Koziris

A Framework for Scheduling Parallel DBMS User-defined Programs on an Attached High-Performance Computer
Michael Kochte, Ramesh Natarajan

Coffee Break
Poster Session Chair: Hitoshi Oi

A Multi-Mode Video-Stream Processor with Cyclically Reconfigurable Architecture
Valeri Kirischian, Vadim Geurkov, Lev Kirischian

An Effective Runtime Scalability Metric to Measure Productivity in High Performance Computing Systems

Jing Du, Xuejun Yang, Zhiyuan Wang

Exploiting the GPU to Accelerate Decision Support Query Execution
Pedro Trancoso, Artemakis Artemiou

Virtual Interacting Network Community: Exploiting Multi-core Architectures to Increase Security
Fabrizio Baiardi, Daniele Sgandurra

Application Based Early Performance Evaluation of SGI Altix 4700 Systems
Subhash Saini, Dennis C. Jespersen, Dale Talcott, Jahed Djomehri, Timothy Sandstrom

Methodology for the Model-Driven Development of Self-Managing Systems
Radu Calinescu

19:30 Welcome Reception  
Tuesday, May 6
Keynote 2 Data-parallel Abstractions for Irregular Programs
Keshav Pingali
Professor, Department of Computer Science
University of Texas at Austin
Coffee Break
Special Session: A Snapshot into the Future, New FP7 Computing Systems Projects Organizers:
Panagiotis Tsarchopoulos, European Commission
Osman Unsal, Barcelona Supercomputing Center

Opening Remarks: European Research in Computing
Panagiotis Tsarchopoulos

HIPEAC: High Performance and Embedded Architecture and Compilation (NOE)
Koen De Bosschere

Apple-Core: Architecture Paradigms and Programming Languages for Efficient programming of multiple CORES (STREP)
Chris Jesshope

CRISP: Cutting edge Reconfigurable ICs for Stream Processing (STREP)
Paul Heysters

Session 4: Innovative Microarchitecture I Chair: Carsten Trinitis

Optimizing Thread Throughput for Multithreaded Workloads on Memory Constrained CMPs
Major Bhadauria, Sally A. McKee

Reducing the Impact of Intra-Core Process Variability with Criticality-Based Resource Allocation and Prefetching
Bogdan F. Romanescu, Michael E. Bauer, Sule Ozev, Daniel J. Sorin

Credit-Based Dynamic Reliability Management using Online Wearout Detection
John Oliver, Rajeevan Amirtharajah, Venkatesh Akella, Frederic T. Chong

Low Power Microarchitecture with Instruction Reuse
Frederico Pratas, Georgi Gaydadjiev, Mladen Berekovic, Leonel Sousa, Stefanos Kaxiras

Lunch Break
A Snapshot into the Future, New FP7 Computing Systems Projects
GENESYS: Generic Embedded System Platform (STREP)
Christian El Salloum

ICT-eMuCo: Embedded Multi-Core Processing for Mobile Communication Systems (STREP)
Attila Bilgic

JEOPARD: Java Environment for Parallel Realtime Development (STREP)
James J. Hunt

Session 5: Innovative Design Chair: Raffaele Trippicione

A Modular 3D Processor for Flexible Product Design and Technology Migration
Gabriel H. Loh

Design of a Spintronic Arithmetic and Logic Unit Using Magnetic Tunnel Junctions
Shruti R. Patil, Xiaofeng Yao, Hao Meng, Jian-Ping Wang, David J. Lilja

Exact Combinational Logic Synthesis and Non-Standard Circuit Design
Paul Tarau, Brenda Luderman

MERASA: Multicore Execution of Hard Real-Time Applications (STREP)
Theo Ungerer

MOSART: Mapping optimisation for Scalable multi-core Architecture, the Cognitive Radio case study (STREP)
Bernard Candaele

VELOX: An Integrated Approach to Transactional Memory on Multi- and Many-core Computers (STREP)
Osman Unsal

Session 6: Compilation Chair: Geppino Pucci

Optimization Strategies for a Java Virtual Machine Interpreter on the Cell Broadband Engine
Kevin Williams, Albert Noll, Andreas Gal, David Gregg

Compiling for an Indirect Vector Register Architecture
Dorit Nuzman, Mircea Namolaru, Ayal Zaks, Jeff H. Derby

Compiler-Directed Frequency and Voltage Scaling for a Multiple Clock Domain Microarchitecture
Arun Rangasamy, Rahul Nagpal, Y.N. Srikant

20:00 Social Dinner
Wednesday, May 7
Keynote 3 JANUS: Reconfigurable High-Performance Computing for Physics
Raffaele Tripiccione
Professor, Department of Physics
Universita' di Ferrara, Italy
Coffee Break
Session 7: Innovative Microarchitecture II Chair: Michela Taufer
Emergent Algorithms for Centroid and Orientation Detection in High-Performance Embedded Cameras
Marcus Komann, Alexander Kröller, Christiane Schmidt, Dietmar Fey, Sandor P. Fekete

Profiling of symmetric encryption algorithms for a novel biomedical-implant architecture
Christos Strydis, Di Zhu, Georgi N. Gaydadjiev

Multi-Terabit IP Lookup using Parallel Bidirectional Pipelines
Weirong Jiang, Viktor K. Prasanna

Improving Single-thread Performance with Fine-grain State Maintenance
Peng Zhou, Soner Onder

Session 8: Innovative Computing Platforms II (GPGPU) Chair: Maria Eleftheriou

Accelerating Advanced MRI Reconstructions on GPUs
Samuel S. Stone, Justin P. Haldar, Stephanie C. Tsao, Wen-mei W. Hwu, Zhi-Pei Liang, Bradley P. Sutton

GPU Acceleration of Cutoff Pair Potentials for Molecular Modeling Applications
Christopher I Rodrigues, David J Hardy, John E Stone, Klaus Schulten, Wen-Mei W Hwu

Cost-Effective Medical Image Reconstruction: From Cluster to Graphics Processing Unit
Maraike Schellmann, Jürgen Vörding, Sergei Gorlatch, Dominik Meiländer

Session 9: Systems Chair: Claudia DiNapoli

Active Storage Revisited: The Case for Power and Performance Benefits for Unstructured Data Processing Applications
Clinton Wills Smullen IV, Shahrukh Rohinton Tarapore, Sudhanva Gurumurthi, Parthasarathy Ranganathan, Mustafa Uysal

Scalable DHT-based Information Service for Large-scale Grids
Hai Jin, Yongcai Tao, Song Wu, Xuanhua Shi

A Distributed Evolutionary Method to Design Scheduling Policies for Volunteer Computing
Trilce Estrada, Olac Fuentes, Michela Taufer

Coffee Break
Closing Remarks
17:30 Conference Adjourns
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