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21st ACM International Conference on Computing Frontiers (CF' 24)
May 7 - 9, 2024, Ischia, Italy
www.computingfrontiers.org
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Important Dates Full Papers
Paper Submission Deadline
Deadline Extended
January 11th, 2024 (AoE)
January 8th, 2024 (AoE)
Author Notification
February 15th, 2024 (extended)
Camera Ready
March 25th, 2024 (AoE)
Submission
Submit your paper
here
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General Co-Chairs
Claudia Di Napoli
ICAR-CNR, IT
Josef Weidendorfer
LRZ / TUM, DE
Program Co-Chairs
Henry Tufo
Colorado University, US
Sarah Azimi
Politecnico di Torino, IT
For more information, visit the website at
www.computingfrontiers.org
Technical Program
Preparing Presentations
The Technical Program of CF24 includes MAIN TRACK SESSIONS and TWO KEYNOTE SPEAKERS, FOUR SPECIAL SESSIONS, and THREE WORKSHOPS.
Guidelines for preparing ORAL PRESENTATIONS (TECHNICAL SESSIONS)
If your paper has been selected for oral presentation, kindly prepare your presentation slides in PDF or PowerPoint format.
The allocated time for formal oral presentations is as follows:
- Full Paper: 25 minutes, including Q&A.
- Short Paper: 15 minutes, including Q&A.
POSTER PRESENTATIONS
If your paper has been chosen for poster presentation, please prepare your poster in A0 portrait format.
During the Blitz Session Poster, each poster will be given a 2-minute pitch.
Program Overview
Detailed Program
Tuesday May 7
| 08:00-08:30 |
Registration Open
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| 08:30-09:00 |
Conference Opening
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| 09:00-10:00 |
Keynote: Processing units in the age of AI
Chair: Henry Tufo, University of Colorado, US |
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Processing units in the age of AI
Pietro Altoe, NVIDIA, Italy |
| 10:00-11:15 |
Session 1: Main Track: Advanced Security and Privacy Tools
Chair: Serena Curzel, Politecnico di Milano |
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MFC-DoH: DoH Tunnel Detection Based on the Fusion of MAML and F-CNN4
Xiaoyu Liu, YiJing Zhang, Xiaodu Yang, Weilin Gai, Bo Sun |
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LeakageFreeSpec-Applying the Wiping Approach to Defend Against Transient Execution Attacks
Fahong Yu, Zhimin Tang, Xiaobo Li, Zhihua Fan |
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DP-Discriminator: A Differential Privacy Evaluation Tool Based on GAN
Yushan Zhang, Xiaoyan Liang, Ruizhong Du, Junfeng Tian |
| 10:00-11:00 |
Special Session: Computer Architecture in Space
Chair: Carsten Trinitis, Technical University of Munich |
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REMPRO: Reconfigurable Modular Processor
Eleonora Vacca, Elio Strollo, Sarah Azimi |
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Assessment of RISC-V Processor Suitability for Satellite Applications
Eleonora Vacca, Giorgio Cora, Sarah Azimi, Luca Sterpone |
| 11:45-13:00 |
Session 2: Main Track: Revolutionizing RISC-V Implementations
Chair: Antonino Tumeo, PNNL, US |
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FazyRV: Closing the Gap between 32-Bit and Bit-Serial RISC-V Cores with a Scalable Implementation
Meinhard Kissich, Marcel Baunach |
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TinyLid: a RISC-V accelerated Neural Network For LiDAR Contaminant Classification in Autonomous Vehicle
Grafika Jati, Martin Molan, Francesco Barchi, Andrea Bartolini, Andrea Acquaviva |
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SeTHet -- Sending Tuned numbers via DMA onto Heterogeneous clusters: an automated precision tuning story
Gabriele Magnani, Daniele Cattaneo, Lev Denisov, Giuseppe Tagliavini, Giovanni Agosta, Stefano Cherubin |
| 11:45-12:45 |
Special Session: Computer Architecture in Space
Chair: Carsten Trinitis, Technical University of Munich |
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The Advanced Particle-astrophysics Telescope: Computation in Space
James Buckley, Jeremy Buhler, Roger Chamberlain |
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A DNN-based Background Segmentation Accelerator for FPGA-equipped satellites
Michele Fiorito, Serena Curzel, Giovanni Gozzi, Fabrizio Ferrandi |
| 14:30-16:00 |
Session 3: Main Track: Innovation in Hardware Design
Chair: Andrea Bartolini, University of Bologna |
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Hardware support for balanced co-execution in heterogeneous processors
Borja Perez, Jose Luis Bosque |
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HLS Taking Flight: Toward Using High-Level Synthesis Techniques in a Space-Borne Instrument
Marion Sudvarg, Chenfeng Zhao, Ye Htet, Meagan Konst, Thomas Lang, Nick Song, Roger D. Chamberlain, Jeremy Buhler, James H. Buckley |
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DNNOPT: A Framework for Efficiently Selecting On-chip Memory Loop Optimizations of DNN Accelerators
Piyumal Ranawaka, Muhammad Waqar Azhar, Per Stenström |
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QuickTree: A Fast Hardware BVH Construction Engine
Yin Su, Hui Guo, Run Yan, Yongwen Wang, Yong Wang, Nong Xiao, Gang Chen, Weihua Zhang, Libo Huang |
| 14:30-15:45 |
Workshop: Malicious Software and Hardware in Internet of Things (MaL-IoT)
Chair: Paolo Palmieri, University College Cork, Ireland, Francesco Regazzoni, University of Amsterdam, The Netherlands, and Università della Svizzera italiana, Switzerland |
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HAGAR: Hashgraph-based Aggregated Communication and Remote Attestation
Jo Vliegen, Md Masoom Rabbani, Wouter Hellemans Nele Mentens |
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On the adoption of PUF for key agreement scheme in Internet of Things
Daniele Lombardi, Mario Barbareschi, Valentina Casola and Antonio Emmanuele |
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X-Factor: Deep Learning-based PCB Counterfeit Detection using X-Ray CT Techniques for Hardware Assurance
Tishya Sarma Sarkar, Shuvodip Maitra, Abhishek Chakraborty, Akashdeep Saha, Joydeep Chowdhury and Debdeep Mukhopadhyay |
| 16:30-18:00 |
Session 4: Main Track: Advanced Techniques in Deep Learning Acceleration
Chair: Corrado De Sio, Politecnico di Torino |
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Denseflex: A Low Rank Factorization Methodology for Adaptable Dense Layers in DNNs
Milad Kokhazadeh, Georgios Keramidas, Vasilios Kelefouras, Iakovos Stamoulis |
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A Lightweight Architecture for Real-Time Neuronal-Spike Classification
Muhammad Ali Siddiqi, David Vrijenhoek, Lennart P. L. Landsmeer, Job van der Kleij, Anteneh Gebregiorgis, Vincenzo Romano, Rajendra Bishnoi, Said Hamdioui, Christos Strydis |
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PEARL: Enabling Portable, Productive, and High-Performance Deep Reinforcement Learning using Heterogeneous Platforms
Yuan Meng, Michael Kinsner, Deshanand Singh, Mahesh Iyer, Viktor Prasanna |
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Fullsparse : A Sparse-Aware GEMM Accelerator with Online Sparsity Prediction
Jiangnan Yu, Yang Fan, Hanfei Wang, Yuxuan Qiao, Xiankui Xiong, Xiao Yao, Haidong Yao, Yechen Zhang, Zheng Wu |
| 16:30-18:00 |
Workshop: Malicious Software and Hardware in Internet of Things (MaL-IoT)
Chair: Paolo Palmieri, University College Cork, Ireland, Francesco Regazzoni, University of Amsterdam, The Netherlands, and Università della Svizzera italiana, Switzerland |
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Relaxed Threshold Implementations
Rim Zahmoul and Vincent Grosso |
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Mal-IoT Panel
Moderators: Paolo Palmieri (University College Cork) and Francesco Regazzoni (University of Amsterdam and Università della Svizzera italiana) |
| 18:00-18:20 |
Blitz Session Poster
Chair: Carsten Trinitis, Technical University of Munich, Eleonora Vacca, Politecnico di Torino |
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Scalable K-Nearest Neighbors Implementation using Distributed Embedded Systems
Corrado De Sio, Andrea Avignone, Luca Sterpone, Silvia Chiusano |
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Multi-Tree Network Protocol Enabling System Partitioning for Shape-Changeable Computer System
Shun Nagasaki, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai |
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MSEU-Net: A Multi-Scale Deep Learning Framework for Precise FHR Baseline Determination
Leya Li, Yu Lu |
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A Portable Tool to Compare Performance Profiles from GPU Offloading Programming Models
Jakob Schäffeler, Bengisu Elis, Amir Raoofy, Josef Weidendorfer, Martin Schulz |
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Hardware Assist for Linux IPC on an FPGA Platform
Lars Nolte, Tim Twardzk, Camille Jalier, Jiyuan Shi, Thomas Wild, Andreas Herkersdorf |
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From Exploit Prediction in the Wild to System-Specific Cyber Security Risk Metrics: Work in Progress
Vladimir Marbukh |
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Enhancing the Robustness of System on FPGA by Routing Isolation
Davide Nicolini, Corrado De Sio, Eleonora Vacca |
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A Novel Robust Core for Detecting Node Failures in FPGA Clusters
Giorgio Cora, Corrado De Sio, Sarah Azimi, Luca Sterpone |
Wednesday May 8
| 09:15-10:30 |
Session 5 : Main Track: Innovation in Heterogeneous Computing
Chair: Amir Raoofy, Leibniz Supercomputing Centre |
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An ANN-Guided Multi-Objective Framework for Power-Performance Balancing in HPC Systems
William Bozzetti Maas, Paulo Souza, Marcelo Caggiani Luizelli, Fabio Rossi, Philippe Navaux, Arthur Lorenzon |
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QR-PULP: Streamlining QR Decomposition for RISC-V Parallel Ultra-Low-Power Platforms
Amirhossein Kiamarzi, Davide Rossi, Giuseppe Tagliavini |
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A Unified CPU-GPU Protocol for GNN Training
Yi-Chien Lin, Gangda Deng, Viktor Prasanna |
| 09:15-10:05 |
Special Session: Semiconductor Manufacturing Initiatives
Chair: Antonino Tumeo, PNNL, US,
Kristian Rietveld, Leiden University, NL |
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Democratization of Computing Innovation via a CHIPS-enabled Renaissance in Co-design
James A. Ang |
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The European Chips Act and its Impact on Teaching
Martin Schulz, Michael Pehl, Carsten Trinitis |
| 10:05-11:15 |
Workshop: Open-Source Hardware Workshop (OSHW24)
Davide Schiavone, Open Hardware Group and Angelo Garofalo, ETH Zurich |
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Using a Performance Model to Implement a Superscalar CVA6
Côme Allart, Jean-Roch Coulon, André Sintzoff, Olivier Potin and Jean-Baptiste Rigaud |
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Seeing Beyond the Order: a LEN5 to Sharpen Edge Microprocessors with Dynamic Scheduling
Michele Caon, Vincenzo Petrolo, Mattia Mirigaldi, Flavia Guella, Guido Masera and Maurizio Martina |
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Integrating SystemC-AMS Power Modeling with a RISC-V ISS for Virtual Prototyping of Battery-operated Embedded Devices
Mohamed Amine Hamdi, Giovanni Pollo, Matteo Risso, Germain Haugou, Alessio Burrello, Enrico Macii, Massimo Poncino, Sara Vinco and Daniele Jahier Pagliari |
| 10:30-11:15 |
Session 6: Main Track: Edge Computing and IoT Optimization II
Chair: Henry Tufo, Colorado University, US |
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HASIIL: Hardware-Assisted Scheduling to Improve IPC Latency in Linux
Tim Twardzik, Lars Nolte, Camille Jalier, Jiyuan Shi, Thomas Wild, Andreas Herkersdorf |
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Computing Economic-Aware Tasks Offloading in MEC-enabled Resource Renting Scenarios
Chao Bu |
| 11:45-13:00 |
Session 7: Main Track: Edge Computing and IoT Optimization I
Chair: Kristian Rietveld, University of Leiden |
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Mini-batching with Fused Training and Testing for Data Streams Processing on the Edge
Reginaldo Luna Junior, Guilherme Cassales, Heitor Gomes, Bernhard Pfahringer, Albert Bifet, Hermes Senger |
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Energy-Aware IoT Deployment Planning
Peiyuan Guan, Animesh Dangwal, Amir Taherkordi, Rich Wolski, Chandra Krintz |
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Register Blocking: An Analytical Modelling Approach for Affine Loop Kernels
Theologos Anthimopoulos, Georgios Keramidas, Vasilios Kelefouras, Iakovos Stamoulis |
| 11:45-13:00 |
Workshop: Open-Source Hardware Workshop (OSHW24)
Chair: Davide Schiavone, Open Hardware Group and Angelo Garofalo, ETH Zurich |
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A Gigabit, DMA-enhanced Open-Source Ethernet Controller for Mixed-Criticality Systems
Chaoqun Liang, Alessandro Ottaviano, Thomas Benz, Mattia Sinigaglia, Luca Benini, Angelo Garofalo and Davide Rossi |
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Implementation and integration of NTT/INTT accelerator on RISC-V for CRYSTALS-Kyber
Alessandra Dolmeta, Emanuele Valpreda, Guido Masera and Maurizio Martina |
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Model theft attack against a tinyML application running on an Ultra-Low-Power Open-Source SoC
Antonio Porsia, Annachiara Ruospo and Ernesto Sanchez |
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Performance evaluation of acceleration of convolutional layers on OpenEdgeCGRA
Nicolò Carpentieri, Juan Sapriza, Davide Schiavone, Daniele Jahier Pagliari, David Atienza Alonso, Maurizio Martina and Alessio Burrello |
| 14:30-16:00 |
Session 8: Main Track: Next-Gen Hardware Acceleration Strategies
Chair: Eleonora Vacca, Politecnico di Torino |
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Clustering and Allocation of Spiking Neural Networks on Crossbar-Based Neuromorphic Architecture
Ilknur Mustafazade, Nagarajan Kandasamy, Anup Das |
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Assessing the Performance of OpenTitan as Cryptographic Accelerator in Secure Open-Hardware System-on-Chips
Emanuele Parisi, Alberto Musa, Maicol Ciani, Francesco Barchi, Davide Rossi, Andrea Bartolini, Andrea Acquaviva |
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TabConv: Low-Computation CNN Inference via Table Lookups
Neelesh Gupta, Narayanan Kannan, Pengmiao Zhang, Viktor Prasanna |
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RV-GEMM: Neural Network Inference Acceleration with Near-Memory GEMM Instructions on RISC-V
Xingbo Wang, Chenxi Feng, Bingzhen Chen, Qi Wang, Yucong Huang, Terry Tao Ye |
| 14:30-16:00 |
Workshop: Open-Source Hardware Workshop (OSHW24)
Chair: Davide Schiavone, Open Hardware Group and Angelo Garofalo, ETH Zurich |
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Stitching FPGA Fabrics with FABulous and OpenLane 2
Leo Moser, Meinhard Kissich, Tobias Scheipel and Marcel Baunach |
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muRISCV-NN: Challenging Zve32x Autovectorization with TinyML Inference Library for RISC-V Vector Extension
Philipp van Kempen, Jefferson Parker Jones, Daniel Mueller-Gritschneder and Ulf Schlichtmann |
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NARS: Neuromorphic Acceleration through Register-Streaming Extensions on RISC-V Cores
Simone Manoni, Paul Scheffler, Alfio Di Mauro, Luca Zanatta, Andrea Acquaviva, Luca Benini and Andrea Bartolini |
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Open-Source Elastic CGRA Generator
Daniel Vázquez, Alfonso Rodríguez and Andrés Otero |
| 16:30-17:20 |
Session 9: Main Track: Advanced Technique in Data Analysis
Chair: Josef Weidendorfer, LRZ / TUM, DE |
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G2A2: Graph Generator with Attributes and Anomalies
Saikat Dey, Sonal Jha, Wu-chun Feng |
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CvTGNet: A Novel Framework for Chest X-Ray Multi-label Classification
Huanwen Liang, Yu Lu, Zhanpeng Xu, Leya Li, Xianghua Fu, Huilin Ge |
| 16:30-18:00 |
Special Session: Collaborative Projects
Chair: Antonino Tumeo, PNNL, US,
Kristian Rietveld, Leiden University, NL |
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Scaling SST for Extreme Scale System Simulation
Ryan Kabrick |
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IO-SEA: Storage I/O and Data Management for Exascale Architectures
Daniel Araújo de Medeiros |
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MYRTUS: Multi-layer 360° dYnamic orchestration and interopeRable design environmenT for compute-continUum Systems
Francesco Regazzoni |
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LIGATE - LIgand Generator and portable drug discovery platform AT Exascale
Gianluca Palermo |
| 17:20-18:00 |
Session 10: Main Track: Next-Gen Networking Innovations
Chair: Serena Curzel, Politecnico di Milano |
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Cookie-Jar: An Adaptive Re-configurable Framework for Wireless Network Infrastructures
Oceane Bel, Burcu O. Mutlu, Joseph Manzano, Cimone Wright-Hamor, Omer Subasi, Kevin Barker |
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Enhancing Bundle Delivery Efficiency in Mobile Ad-hoc Networks with a Multi-protocol Delay-Tolerant Network
Olivia Nakayima, Mostafa l. Soliman, Kazunori Ueda, Samir A. Elsagheer |
| 18:30-22:00 |
SOCIAL DINNER
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Thursday May 9
| 09:00-10:00 |
Keynote: First Exascale Flow Simulations of Fission and Fusion Energy Systems
Chair: Henry Tufo, University of Colorado, US |
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First Exascale Flow Simulations of Fission and Fusion Energy Systems
Elia Merzari, Pennsylvania State University, US |
| 10:00-11:15 |
Session 11: Main Track: GPU Acceleration Techniques
Chair: Biagio Cosenza, Università di Salerno, I |
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Sparse MTTKRP Acceleration for Tensor Decomposition on GPU
Sasindu Wijeratne, Viktor K Prasanna, Kannan Rajgopal |
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BLP: Block-Level Pipelining for GPUs
Wu-chun Feng, Xuewen Cui, Thomas Scogland, Bronis de Supinski |
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ApGraph: An Approximate Workflow for Iterative Graph Processing on GPU
Ruifeng Wang, Li Shen |
| 10:00-11:15 |
Special Session: Quantum Computing
Chair: Anastasiia Butko, LBNL, CA |
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HamPerf: A Hamiltonian-Oriented Approach to Quantum Benchmarking
Anastasiia Butko, Katherine Klymko, Daan Camps, Nicolas Sawaya |
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From the Physics Lab to the Computer Lab: Towards a Flexible and Comprehensive DevOps for Quantum Computing
Hossam Ahmed, Xiaolong Deng, Jorge Echavarria, Mathias Gammelmark, Sven Karlsson, Michal Reznak, Laura Brandon Schulz, Martin Schulz, Matthew Tovey |
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Invited talk: Quantum computer simulation on HPC
Nobuyasu Ito, Naoki Yoshioka |
| 11:45-13:00 |
Session 12: Main Track: Quantum Computing I
Chair: Martin Schulz, TUM |
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Trainability Barriers in Low-Depth QAOA Landscapes
Joel Rajakumar, John Golden, Andreas Bärtschi, Stephan Eidenben |
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Quantum Circuit Cutting Minimising Loss of Qubit Entanglemen
Michael Hart, John McAllister |
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Replication-Based Quantum Annealing Error Mitigation
Hristo Djidjev |
| 11:45-13:00 |
Workshop Compiler Frontiers
Chair: Antonino Tumeo, PNNL, US,
Kristian Rietveld, Leiden University, NL |
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A General Purpose Analog Computer to Population Protocol Compiler
Xiang Huang and Andrei Migunov |
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Compile-Time Optimization of the Energy Consumption of Numerical Computations
Dorra Ben Khalifa and Matthieu Martel |
| 14:30-15:50 |
Session 13: Main Track: Quantum Computing II
Chair: Martin Schulz, TUM |
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Reconstructing Cut Quantum Circuits Maximising Fidelity between Quantum States
Michael Hart, John McAllister |
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Evaluation of Quantum and Hybrid Solvers for Combinatorial Optimization
Amedeo Bertuzzi, Davide Ferrari, Antonio Manzalini, Michele Amoretti |
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Quantum Dynamic Frame of Computational Intelligence Algorithm
Fang Wang, Peng Wang |
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Beyond the Buzz: Strategic Paths for Enabling Useful NISQ Applications
Pratibha Raghupati Hegde, Oleksandr Kyriienko, Hermanni Heimonen, Panagiotis Tolias, Gilbert Netzer, Panagiotis Barkoutsos, Ricardo Vinuesa, Ivy Peng, Stefano Markidis |
| 14:30-15:45 |
Workshop Compiler Frontiers
Chair: Antonino Tumeo, PNNL, US,
Kristian Rietveld, Leiden University, NL |
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Effective HPC Programming via Domain-Specific Abstractions and Compilation
Gokcen Kestor |
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High-level synthesis for complex applications: the Bambu approach
Fabrizio Ferrandi |
| 15:50-16:15 |
Award Ceremony and Closing
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