Computing Frontiers 2010

Final Program

Sunday, May 16

Intel Parallel Programming Workshop co-located with CF 2010
Opening Reception

Monday, May 17

08:50 Welcome
  Session I (Neuroscience)
Session Chair: Paul H J Kelly (Imperial College)
09:00 Towards Chip-on-Chip Neuroscience: Fast Mining of Neuronal Spike Streams Using Graphics Hardware
Yong Cao, Debprakash Patnaik, Sean Ponce, Jeremy Archuleta, Patrick Butler, Wu-chun Feng, Naren Ramakrishnan
09:25 SpiNNaker: Effects of Traffic Locality and Causality on the Performance of the Interconnection Network
Javier Navaridas, Luis Plana, Jose Miguel-Alonso, Mikel Lujan, Steve Furber
09:50 Scalable Event-Driven Native Parallel Processing: The SpiNNaker Neuromimetic System
Alexander Rast, Cameron Patterson, Xin Jin, Mukaram Khan, Steve Furber, Francesco Galluppi
10:15 Coffee break
  Session II (Operating Systems and Storage)
Session Chair: Luciano Margara (University of Bologna)
10:35 Operating System Support for Mitigating Software Scalability Bottlenecks on Asymmetric Multicore Processors
Juan Carlos Saez, Alexandra Fedorova, Manuel Prieto, Hugo Vegas
11:00 Efficient Cache Design for Solid-State Drives
Miaoqing Huang, Olivier Serres, Vikram K. Narayana, Tarek El-Ghazawi, Gregory Newby
11:30 Keynote I
Session Chair: Nancy M Amato (Texas A&M University)
  Programmable Matter with Self-reconfiguring Robots
Daniela Rus (MIT)
12:30 Lunch
  Session III (Concurrency and Scheduling)
Session Chair: Cecilia Metra (University of Bologna)
14:00 Supporting Lock-Free Composition of Concurrent Data Objects
Daniel Cederman, Philippas Tsigas
14:25 Collaborative Scheduling of DAG Structured Computations on Multicore Processors
Yinglong Xia, Viktor K. Prasanna
  Session IV a (Poster presentation)
Session Chair: Pedro Trancoso (University of Cyprus)
14:50 Poster lightning talks, 3 min a poster, 12 posters
  Efficient and Scalable Barrier Synchronization for Many-Core CMPs
José L. Abellán, Juan Fernández, Manuel E. Acacio
  A communication infrastructure for a million processor machine
Andrew Brown, Steve Furber, Jeff Reeve, Peter Wilson, Mark Zwolinski, John Chad, Luis Plana, David Lester
  A Hyperscalar Multi-core Architecture
Jih-Ching Chiu, Yu-Liang Chou
  Augmenting Cache Partitioning with Thread-Aware Insertion/Promotion Policies to Manage Shared Caches
Xiufeng Sui, Junmin Wu, Guoliang Chen, Yixuan Tang, Xiaodong Zhu
  Performance and Power Evaluation of an In-line Accelerator
Alejandro Rico, Jeff H. Derby, Robert K. Montoye, Timothy H. Heil, Chen-Yong Cher, Pradip Bose
  Energy Efficient Biomolecular Simulations with FPGA-based Reconfigurable Computing
Ananth Nallamuthu, Scott Hampton, Melissa C. Smith, Sadaf R. Alam, Pratul K. Agarwal
  Efficient Implementation of GPGPU Synchronization Primitives on CPUs
Jayanth Gummaraju, Ben Sander, Laurent Morichetti, Benedict Gaster, Lee Howes
  Efficient pattern matching on GPUs for intrusion detection systems
Antonino Tumeo, Oreste Villa, Donatella Sciuto
  Efficient Parallel Implementation of Multilayer Backpropagation Network on Torus-connected CMPs
X. Jin, M. Lujan, M.M. Khan, L.A. Plana, A.D. Rast, S.R. Welbourne, S.B. Furber
  Porting existing cache-oblivious Linear Algebra HPC Modules to Larrabee Architecture
Alexander Heinecke, Carsten Trinitis, Josef Weidendorfer
  Novel Low-Cost Aging Sensor
Martin Omana, Daniele Rossi, Nicolò Bosio, Cecilia Metra
  A High-Speed AES Architecture Implementation
Flavius, Mircea, Lucian, Mihai
15:30 Coffee break
  Session IV b (Poster presentation)
16:00 Poster lightning talks, 3 min a poster, 13 posters
  A Predictable Communication Assist
Ahsan Shabbir, Sander Stuijk, Akash Kumar, Bart Theelen, Bart Mesman, Henk Corporaal
  A Predictable Communication Assist
Ahsan Shabbir, Sander Stuijk, Akash Kumar, Bart Theelen, Bart Mesman, Henk Corporaal
  Exploitation of Nested Thread-Level Speculative Parallelism on Multi-Core Systems
Arun Kejariwal, Milind Girkar, Xinmin Tian, Hideki Saito, Alex Nicolau, Alex Veidenbaum, Utpal Banerjee, Constantine Polychronopoulos
  From Volunteer to Cloud Computing: Cloud@Home
Vincenzo D. Cunsolo, Salvatore Distefano, Antonio Puliafito, Marco Scarpa
  Design of a Cloud Naming Framework
Antonio Celesti, Massimo Villari, Antonio Puliafito
  A Service Based Approach for the Execution of Scientific Workflows in Grids
Andrea Bosin, Nicoletta Dessì, Madusudhanan Bairappan
  Variability-tolerant Run-time Workload Allocation for MPSoC Energy Minimization under Real-time Constraints
Francesco Paterna, Andrea Acquaviva, Alberto Caprara, Francesco Papariello, Giuseppe Desoli, Luca Benini
  A Portable Parallel Finite Element Simulation System
Yufeng Nie, Lei Wang, Weiwei Zhang
  Low Cost and Low Intrusive Approach to Test On-Line the Scheduler of High Performance Microprocessors
Daniele Rossi, Martin Omana, Gianluca Berghella, Cecilia Metra, Abhijit Jas, Chandra Tirumurti, Rajesh Galivanche
  Automatic Tuning of MPI Runtime Parameter Settings by Using Machine Learning
Simone Pellegrini, Thomas Fahringer, Herbert Jordan, Hans Moritsch
  Exposing Parallelism and Locality in a Runtime Parallel Optimization Framework
David A. Penry, Daniel J. Richins, Tyler S. Harris, David Greenland, Koy D. Rehme
  Erbium: A Deterministic, Concurrent Intermediate Representation for Portable and Scalable Performance
Cupertino Miranda, Philippe Dumont, Albert Cohen, Marc Duranton, Antoniu Pop
Poster Session and Reception

Tuesday, May 18

  Session V (Caches and Branches 1)
Session Chair: Josef Weidendorfer (TU München)
09:00 NCID: A Non-inclusive Cache, Inclusive Directory Architecture for Flexible and Efficient Cache Hierarchies
Li Zhao, Ravi Iyer, Srihari Makineni, Don Newell
09:25 Global Management of Cache Hierarchies
Mohamed Zahran, Sally A. McKee
09:50 Where replacement algorithms fail: a thorough analysis
Georgios Keramidas, Pavlos Petoumenos, Stefanos Kaxiras
10:15 Coffee break
  Session VI (Caches and Branches 2)
Session Chair: Carsten Trinitis (TU München)
10:35 Dynamic Load Balancing Through Cache Allocation
Miquel Moreto, Francisco J. Cazorla, Rizos Sakellariou, Mateo Valero
11:00 EXACT: Explicit Dynamic-Branch Prediction with Active Updates
Muawya Al-Otoom, Elliott Forbes, Eric Rotenberg
11:30 Keynote II
Session Chair: Gianfranco Bilardi (Università di Padova)
  Nature-Inspired Techniques for Self-Organization in Dynamic Networks
Ozalp Babaoglu (University of Bologna)
12:30 Lunch
  Session VII (Parallel Systems)
Session Chair: Thomas Gross (ETH Zurich)
14:00 Hybrid Parallel Programming with MPI and Unified Parallel C
James Dinan, P. Sadayappan, Pavan Balaji, Ewing Lusk, Rajeev Thakur
14:25 A Heterogeneous Parallel System Running Open MPI on a Broadband Network of Embedded Set-Top Devices
Richard Neill, Alexander Shabarshin, Luca P. Carloni
14:50 Variant-based Competitive Parallel Execution of Sequential Programs
Oliver Trachsel, Thomas Gross
15:15 Enabling a highly-scalable global address space model for petascale computing
Vinod Tipparaju, Edoardo Apra, Weikuan Yu, Jeffery Vetter
15:40 Coffee break
  Session VIII (Processor Architecture)
Session Chair: Sally McKee (Chalmers University of Technology)
16:00 On-chip Communication and Synchronization Mechanisms with Cache-Integrated Network Interfaces
Stamatis Kavadias, Manolis Katevenis, Michail Zampetakis, Dimitrios Nikolopoulos
16:25 Models for Generating Locality-Tuned Traveling Threads for a Hierarchical Multi-level Heterogeneous Multicore
Patrick A. La Fratta, Peter M. Kogge
16:50 Proposition for a sequential accelerator in future general-purpose manycore processors and the problem of migration-induced cache misses
Pierre Michaud, Yiannakis Sazeides, Andre Seznec
17:45 Depart for excursion

Wednesday, May 19

  Session IX (Quantum Computing)
Session Chair: Steve Furber (University of Manchester)
09:00 An Improved Quantum Query Algorithm for Computing AND Boolean Function
Taisia Mischenko-Slatenkova, Alina Vasilieva
09:25 Reversible Online BIST Using A Bidirectional BILBO
Dilip Vasudevan, Jioyan Chen, Emanuel Popovici, Michel Schellekens
  Session X (Power 1)
Session Chair: Monica Alderighi (INAF)
09:50 Power and Performance Optimization of Voltage/Frequency Island-Based Networks-on-Chip Using Reconfigurable Synchronous/Bi-Synchronous FIFOs
Amir-Mohammad Rahmani, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen
10:15 Applying Statistical Machine Learning to Multicore Voltage & Frequency Scaling
Michael Moeng, Rami Melhem
10:40 Coffee break
  Session XI (Power 2)
Session Chair: Roberto Gioiosa (BSC)
11:00 Interval Based Models for Run-Time DVFS Orchestration in SuperScalar Processors
Georgios Keramidas, Vasilis Spiliopoulos, Stefanos Kaxiras
11:25 Multiple Sleep Modes Leakage Control in Peripheral Circuits of a All Major SRAM-Based Processor Units
Houman Homayoun, Avesta Sasan, Aseem Gupta, Alex Veidenbaum, Fadi Kurdahi, Nikil Dutt
11:50 Towards Greener Data Centers with Storage Class Memory: Minimizing Idle Power Waste through Coarse-Grain Management in Fine-Grain Scale
In Hwan Doh, Young Jin Kim, Jung Soo Park, Eunsam Kim, Jongmoo Choi, Donghee Lee, Sam H. Noh
12:30 Lunch
  Session XII (Fault Tolerance and Parallel Applications)
Session Chair: Andreas Liehr (Universität der Bundeswehr München)
14:00 Protective Redundancy Overhead Reduction Using Instruction Vulnerability Factor
Demid Borodin, B.H.H. (Ben) Juurlink
14:25 Self-organization on a Swarm Computing Fabric: a new way to look at fault tolerance
Danilo Pani, Simone Secchi, Luigi Raffo
14:50 Dynamic Load Management of MMOGs in Distributed Environments
Herbert Jordan, Radu Prodan, Vlad Nae, Thomas Fahringer
15:15 Scalable Simulation of Complex Network Routing Policies
Andrew Stone, Michelle Strout, Steven DiBenedetto, Daniel Massey
15:40 Closing remarks
last modified: 2010/04/05