Agenda of Intel Parallel Programming Workshop

The workshop will take place on 16th March 2010!

Please register here: www.teachparallelseminar.com

2.00 – 2.40 pm	Introduction: Why Parallel Programming is a Critical Skill for All the Sciences Intel engineer will discuss how current trends in processors design will lead to increasing core counts and how programmers must address scalability in software development.
2.40 – 3.00 pm	The Intel® Academic Community Why every Professor in Technology should be a Member? Intel community manager takes you on a tour of the Academic Community website and explains the benefits of membership including free access to world-class technical content from both Intel and Academic Community members, free development tools for Academics, etc.
3.00 – 3.40 pm	Intel’s Multicore Testing Lab How Your University Can Get Access. Intel engineer will not only demonstrate our remote on-line system for scalability research and how various software tools can be used to test your programs scalability, but also explain how Academic Community members can get access to this 32-core system for research and curriculum development. Include a success point for this one case study
3.40 – 4.10 pm	Break: The 3 C’s - Coffee, Cookies and Canapés
4.10 – 5.40 pm	Integrating Parallel Programming into University Curricula
	How We Are Doing IT at Technische Universität München Professor Carsten Trinitis will share his personal experience in not only identifying key lessons and where they fit in TUM’s curriculum, but also issues encountered in getting the changes made to the courses at his school and a student of his Alexander Heinecke, will give his (student) perspective on his experiences studying multicore and parallel programming at TUM. How We Are Doing IT at ETH Zürich Professor Thomas Gross from ETH Zürich will share his personal experience in not only identifying key lessons and where they fit in ETH Zürich’s curriculum, but also issues encountered in getting the changes made to the courses at his school.
5.40 – 6.00 pm	Break: Caffeine, sugar and a little grease to power you through until the conference dinner.
6.00 – 7.00 pm	Panel Discussion 3 panellists will discuss the Challenges to Curriculum Adoption. Thomas Gross will chair a panel discussion on teaching parallel programming and encourage all participants to provide feedback on what assistance their universities need to make the transition to teaching parallel programming in their undergraduate curriculum.

For more information, please see: www.teachparallelseminar.com

Keynote

There will be a Keynote held by Faye Briggs (Intel Corporation)

Faye Briggs

Faye riggs is an Intel Fellow and Director of Scalable Server Architecture for the Data Center Group, in Intel Architecture Group. He is responsible for ensuring that Intel.s multi-core and many-core-based server architectures achieve leading performance.

Briggs has had a leadership role in developing multiple generations of innovative multiprocessor server and chipset designs, including all front-side-bus based Xeon dual and multiprocessor server chipsets and platform architectures. He conceptualized the first Intel point-to-point coherent scalability port for 2P . 16P scalable architecture family of 870 server chipsets for Itanium and Xeon servers and led the development of the chipset.

Prior to joining Intel in 1997, Briggs held various positions at Sun Microsystems, including serving as the co-architect of Sun.s original SPARC processor. Briggs was also a co-founder and CTO of Axil Computers, where he led the development of chipsets, boards and systems for more than 30 servers, storage and workstation products. He also served as a tenured associate professor at Rice University and as a faculty member at Purdue University, both in electrical and computer engineering.

Briggs has published numerous technical papers on processor and multiprocessor architectures, memory ordering, cache coherence and system performance. He is the co-author of the McGraw-Hill published textbook, .Computer Architecture and Parallel Processing.. Briggs received an Intel Achievement Award for the successful definition and execution of Intel.s first quad-core products.

Briggs received his bachelor.s degree in electrical engineering from Ahmadu Bello University, Nigeria. He received his master.s degree in electrical engineering from Stanford University, and his doctorate in electrical and computer engineering from the University of Illinois, Urbana-Champaign in 1977.

last modified: 2010/05/11