Key Dates

Submissions Deadline

Febrary 5, 2017 AOE
January 20, 2017

Author Notification

March 14, 2017

Camera-Ready Papers Due

April 4, 2017


Submit your paper here

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Previous Conferences

2016, 2015, 2014, 2013, 2012, 2011, 2010, 2009, 2008, 2007, 2006, 2005, 2004

General Chair

Roberto Giorgi
University of Siena, IT

Program Co-Chairs

Michela Becchi
North Carolina State University, US
Francesca Palumbo
University of Sassari, IT

For more information, visit the website at
Computing Frontiers 2017 is proud to announce the following keynote speakers and talks this year:
  • Keynote 1: Mateo Valero
    Runtime Aware Architectures
  • Keynote 2: Mark Robins
    The Future of Deep Learning: Challenges & Solutions

Runtime Aware Architectures

Mateo Valero, Computer Architecture Department — UPC Barcelona

In the last years the traditional ways to keep the increase of hardware performance to the rate predicted by the Moore's Law vanished. When uni-cores were the norm, hardware design was decoupled from the software stack thanks to a well defined Instruction Set Architecture (ISA). This simple interface allowed developing applications without worrying too much about the underlying hardware, while computer architects proposed techniques to aggressively exploit Instruction-Level Parallelism (ILP) in superscalar processors. Current multi-cores are designed as simple symmetric multiprocessors on a chip. While these designs are able to compensate the clock frequency stagnation, they face multiple problems in terms of power consumption, programmability, resilience or memory. The solution is to give more responsibility to the runtime system and to let it tightly collaborate with the hardware. The runtime has to drive the design of future multi-cores architectures. In this talk, we introduce an approach towards a Runtime-Aware Architecture (RAA), a massively parallel architecture designed from the runtime's perspective.


Mateo Valero is a professor in the Computer Architecture Department at UPC, in Barcelona. His research interests focuses on high performance architectures. He has published approximately 700 papers, has served in the organization of more than 300 International Conferences and he has given more than 500 invited talks. He is the director of the Barcelona Supercomputing Centre, the National Centre of Supercomputing in Spain.

Dr. Valero has been honoured with several awards. Among them, Seymour Cray Award, one of the IEEE Computer Society’s highest awards in contributions to high-performance computing; the Eckert-Mauchly Award, one of the IEEE-ACM highest awards in contributions to computer architectures; Harry Goode Award; ACM Distinguished service; Euro-Par Achievement Award; the "King Jaime I" in research and two National Awards on Informatics and on Engineering. He has been named Honorary Doctor by 9 Universities.  "Hall of the Fame" member of the IST European Program (selected as one of the 25 most influents European researchers in IT during the period 1983-2008. Lyon, November 2008).

Fellow of IEEE, ACM, Intel Distinguished Research Fellow. Member of Royal Spanish Academy of Engineering, Royal Academy of Science and Arts, correspondent academic of Royal Spanish Academy of Sciences, Academia Europaea and Mexican Academy of Science.

In 1998 he won a “Favourite Son” Award of his home town, Alfamén (Zaragoza) and in 2006, his native town of Alfamén named their Public College after him.

The Future of Deep Learning: Challenges & Solutions

Mark Robins, Intel Nervana

Mark will begin with a brief overview of deep learning and what has led to its recent popularity. He will provide a few demonstrations and examples of deep learning applications based on recent work at Intel Nervana.

He will explain some of the challenges to continued progress in deep learning — such as high compute requirements and lengthy training time — and will discuss some of the solutions (e.g. custom deep learning hardware) that Intel Nervana is developing to usher in a new era of even more powerful AI.


Mark Robins is Head of Products for Intel’s Artificial Intelligence Products Group. Mark was Vice President of Products at Nervana prior to its acquisition by Intel in August 2016.

Prior to Nervana, Mark served as VP Product for Influitive and, before that, as VP Product for Chegg through their IPO in 2013. Before Chegg, Mark was co-founder/CEO of Grouply, a social networking startup funded by Reid Hoffman and O’Reilly Alphatech Ventures that was acquired in 2010. Before Grouply, Mark was Sr. Director of Product Management at Siebel Systems through its acquisition by Oracle in 2006. Mark started his career as a satellite communications systems engineer for Hughes Aircraft Company, which is now part of Boeing. Mark earned a BS and MS in electrical engineering from Cornell and Caltech, respectively, where he also studied neural networks. Mark holds an MBA from Harvard Business School.