Key Dates

Submissions Deadline

Febrary 5, 2017 AOE
January 20, 2017

Author Notification

March 14, 2017

Camera-Ready Papers Due

April 4, 2017


Submit your paper here

Download CFP

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Previous Conferences

2016, 2015, 2014, 2013, 2012, 2011, 2010, 2009, 2008, 2007, 2006, 2005, 2004

General Chair

Roberto Giorgi
University of Siena, IT

Program Co-Chairs

Michela Becchi
North Carolina State University, US
Francesca Palumbo
University of Sassari, IT

For more information, visit the website at


Computing Frontiers 2017 will feature three co-located workshops. Submission of papers to the workshops is handled separately from the main conference. Please refer to the websites of the workshops for more details.

Big Data Analytics (BigDAW '17)

Aim and Scope:
Managing and processing large volumes of data, or “Big Data”, and gaining meaningful insights is a significant challenge facing the distributed computing community; as a consequence, many business are demanding large scale streaming data analytics. This has significant impact in a wide range of domains including health care, bio-medical research, Internet search, finance and business informatics, and scientific computing.

Despite considerable advancements on high performance, large storage, and high computation power, there are challenges in identifying, clustering, classifying, and interpreting of a large spectrum of information.

The purpose of this workshop is to provide a fertile ground for collaboration between research institutions and industries and in analytics, machine learning, and high performance computing.

Workshop Organizers:

    Roberta Piscitelli (, NL)
    Giovanni Mariani (IBM Research, NL)
Workshop Website:
Paper Submission Deadline: February 24, 2017
Decision Notification: March 30, 2017
Camera-Ready Papers Due: April 4, 2017

Design of Low Power Embedded Systems (LP-EMS '17)

Aim and Scope:
Modern cyber-physical and highly networked systems impose to designers challenging and conflicting requirements. Implementing real-time high-performance systems and minimizing, contemporarily, their power consumption is not straightforward. Emergent and unpredictable behaviours require these systems to adapt at runtime to mutable conditions. Therefore, advanced modelling strategies as well as efficient design automation techniques should be capable of optimizing complex parallel applications over heterogeneous multi- and many-cores platforms. Complexity on algorithmic side and heterogeneity on hardware side are colliding system constraints, which can be tackled by adopting hw/sw co-design solutions and flexible design frameworks.

With respect to this context, contributions are expected in different fields of digital signal processing such as: telecommunication, multimedia, medical imaging, computing graphics, biomedical applications and many others!

Papers may include, but are not limited to, the following topics:

  • High-level synthesis and hw/sw co-design techniques for low-power digital signal/image processing;
  • Design of self-energy aware systems;
  • Design space exploration techniques, with special emphasis on power/energy estimations and power minimization methodologies;
  • Parallel/high throughput processing techniques for low-power digital signal/image processing;
  • Algorithm-level optimization, low-complexity algorithm for low-power digital signal/image processing;
  • Approximate computing, low power arithmetic
  • MPEG Green Metadata;
  • Dynamic voltage and frequency scaling, hw and sw dynamic power management.

Workshop Organizers:

    Francesco Conti, Integrated Systems Laboratory - ETH Zurich and Energy-Efficient Embedded Systems Laboratory - University of Bologna
    Paolo Meloni, Microelectronics and Bioengineering Lab - University of Cagliari
    Daniel Menard, Institut National des Sciences Appliquées de Rennes
Workshop Website:
Abstract due: March 3, 2017 (extended deadline)
Submission due: March 5, 2017 (extended deadline)
Notification of acceptance/rejection: March 21, 2017
Submission of camera-ready papers and registration: April 6, 2017

Malicious Software and Hardware in Internet of Things (MaL-IoT '17)

Aim and Scope:
Cyber-physical and smart embedded systems, already highly networked, will be even more connected in the near future to form the Internet of Things, handling large amounts of private and safety critical data. The pervasive diffusion of these devices will create several threats to privacy and could open new possibilities for attackers, since the security of even larger portions of the Internet of Things could be harmed by compromising a reduced number of components. The possibility of securely updating devices should be guaranteed and it should be possible to verify and assert the root of trust of components. With respect to this context we expect contributions in different areas of security in Internet of Things. Topics of the workshop include but are not limited to:

  • Malicious firmware design and detection
  • Malware in Internet of Things applications
  • Hardware root of trust
  • Privacy issues of smart-home systems and complex systems
  • Hardware Trojans and their effects on systems
  • Hardware authentication and IP protection
  • Secure communication and key-management
  • Implementation attacks and countermeasures
  • Emerging threats and attack vectors in the Internet of Things
  • Supply chain security
  • Physical threats in Cyber-Physical Systems

Workshop Organizers:

    Georg T. Becker, Ruhr-University Bochum, DE,
    Francesco Regazzoni, ALaRI - USI, CH,
Workshop Website:
Submissions Deadline: February 10, 2017
Author Notification: March 17, 2017
Camera-Ready Papers Due: March 25, 2017