Key Dates Full Papers
Abstract Submission Deadline
February 6th, 2022 (AoE) (Extended)
Paper Submission Deadline
February 13th, 2022 (AoE) (Extended)
Author Notification
March 22th, 2022
Final Papers Due
April 8th, 2022 (AoE) (Extended)
Key Dates Posters
Paper Submission Deadline
April 3rd, 2022
Author Notification
April 5th, 2022
Final Papers Due
April 8th, 2022
Submission
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here
Submit your poster
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General Chair
Luca Sterpone
Politecnico di Torino, Italy
For more information, visit the website at
www.computingfrontiers.org
Computing Frontiers 2022 is proud to announce the following keynote
speakers and talks this year:
- Keynote 1:
Riccardo Mariani, VP of Industry Safety, NVIDIA
How End-to-end Computing & Safety Bring Autonomous Machines to Life
- Keynote 2:
José E. Moreira, IBM Thomas J. Watson Research Center
High-Performance Computing in the Enterprise: A Look Inside a Modern Business-Oriented Processor
How End-to-end Computing & Safety Bring Autonomous Machines to Life
Riccardo Mariani, VP of Industry Safety, NVIDIA
Abstract:
This talk will delve into the role end-to-end computing and safety play in bringing autonomous machines to fruition. We’ll explore how GPUs, artificial intelligence and new safety standardizations are essential to creating a safe and secure autonomous future.
Bio:
Riccardo Mariani is widely recognized as an expert in functional safety and integrated circuit reliability. In his current role as VP of Industry Safety at NVIDIA, he is responsible for driving safety alignment across NVIDIA’s automotive and embedded business units. To this end, he is responsible for developing cohesive safety strategies and cross-segment safety processes, architecture, and products that can leveraged across NVIDIA’s AI-based hardware and software platforms. Prior to NVIDIA, he was chief functional safety technologist at Intel Corporation, where he oversaw strategies and technologies for IoT applications that require functional safety, high reliability, and performance, such as autonomous driving, transportation and industrial systems. Riccardo Mariani is 2021 First VP of IEEE Computer Society and also chair of the IEEE Computer Functional Safety Standards Committee. Mariani spent the bulk of his career as CTO of Yogitech, an industry leader in functional safety technologies. Before co-founding the Italian company in 2000, he was technical director at Aurelia Microelettronica, where his responsibilities included leading high-reliability topics in projects with CERN in Geneva. A prolific author and respected inventor in the functional safety field, Mariani has contributed to multiple industry standards efforts throughout his career, including leading the ISO 26262-11 part specific to semiconductors and now co-editing ISO/TR 5469 on Artificial Intelligence and Safety. He is the recipient of the 2021 Ron Waxman DASC Meritorious Service Award. He holds a bachelor’s degree in electronic engineering and a Ph.D. in microelectronics from the University of Pisa in Italy.
High-Performance Computing in the Enterprise: A Look Inside a Modern Business-Oriented Processor
José E. Moreira, IBM Thomas J. Watson Research Center
Abstract:
Modern business-oriented processors have to address a broader spectrum of computations that ever before. In addition to the more traditional business applications, such as transaction processing and web serving, these processors are expected to perform heavy computations in support of business analytics. Examples of such computations include graph algorithms, classical machine learning, deep learning, and computational finance. The numerical processing requirements of those computations can be similar to those in the scientific and engineering domains. But business computations also have their own requirements, including security, cryptography, compliance, and even differences in data that cause unique behavior in the enterprise environment. In this talk, we will take a look at a modern business-oriented processor, the IBM POWER10. This processor is built on a balance of computation capability and interconnection bandwidth. The system infrastructure support configurations with up to 16 processor chips and up to 1920 simultaneous threads of execution, as well as an expansive memory system with up to 2 Petabytes of addressing space. The POWER10 processing core has been significantly enhanced over its predecessors, including improved vector processing and an all-new matrix math engine. The processor has also been augmented with new security features, including protection against return-oriented programming attacks. We will use POWER10 as an example of what a modern business-oriented processor must deliver and we will discuss directions for future versions of this processor, which will face even more demanding operational requirements.
Bio:
José E. Moreira is a Distinguished Research Staff Member at the IBM Thomas J. Watson Research Center. He received a B.S. degree in physics and B.S. and M.S. degrees in electrical engineering from the University of Sao Paulo. He received a Ph.D. degree in electrical engineering from the University of Illinois at Urbana-Champaign. Since joining IBM in 1995, Dr. Moreira has worked on a variety of high-performance systems, including two ASCI systems (Blue Pacific and White) and the Blue Gene/L supercomputer, for which he was the System Software architect. Dr. Moreira has been responsible for various architectural and micro-architectural innovations in the three most recent generations of POWER processors. He conceived the POWER10 matrix unit, the first of its kind in a commercial processor. Dr. Moreira is a Fellow of the IEEE (Institute of Electrical and Electronics Engineers) and a Distinguished Scientist of the ACM (Association for Computing Machinery). Contact him at jmoreira@us.ibm.com.
